1. Field of the Invention
The present invention relates to a semiconductor package and a method for fabricating a semiconductor package.
2. Description of the Related Art
A typical ball grid array (BGA) semiconductor package includes a semiconductor chip mounted on an upper surface of an insulative, printed circuit board substrate. The substrate may be made of a glass fiber filled organic laminate, such as FR4 board, FR5 board, or BT board, and has interconnected, conductive circuit patterns on upper and lower surfaces thereof. A hardened encapsulant material covers the chip, the upper surface of the substrate, and electrical conductors, such as bond wires, that extend between the chip and the circuit patterns on the upper surface of the substrate. Conductive balls or other input/output terminals are formed on the circuit patterns of the lower surface of the substrate.
Consistent with a trend toward smaller and thinner packages, the semiconductor chip is sometimes mounted within a central aperture of the substrate. The chip is supported in the aperture by the hardened encapsulant material. One difficulty with such a package, however, is warpage of the substrate due in part to temperature cycling during the manufacturing process and differences in the thermal expansion properties of the various materials of the package, e.g., differences in the thermal expansion properties of the substrate and encapsulant material. The warpage is particularly manifest at the corners of the package. Where the package substrate is warped, the conductive balls or other input/output terminals on the lower surface of the substrate are uneven. This causes difficulty when mounting the package on a motherboard. The magnitude of the warpage tends to increase as package size increases, and thus tends to impose an upper limit on the package size.
The present invention includes, among other things, a substrate for a semiconductor package that is resistant to the warpage problem mentioned above, a method of making such a package, and a circuit board strip for making a plurality of the packages in a parallel process.
For example, one embodiment of a semiconductor package in accordance with the present invention includes a semiconductor chip attached to a circuit board. For instance, the chip may be provided within a central aperture of the circuit board, and held therein by hardened encapsulant material. Circuit patterns are provided on one or both of two opposing major surfaces of the circuit board. The chip is electrically connected to the circuit patterns of one of the surfaces through bond wires, leads, or the like. The circuit patterns of at least one of the surfaces include input/output terminals for the package, which are in electrical communication through the various package elements to the chip. The terminals may include conductive balls, as in a BGA package, or exposed lands, as in a land grid array (LGA) package, among other possibilities. The encapsulating material covers the chip and the electrical connections. The circuit board further includes at least one lateral slot through the circuit board. The slot(s) may extend inward from an outer peripheral wall of the circuit board or, in the case where the circuit board includes a central aperture, may extend outward from the central aperture, or both. The one or more slots act to relieve stresses in the circuit board that are otherwise manifested in warpage. Such stresses can result from temperature cycling typically during the manufacturing process, the encapsulation process, and/or differing thermal expansion properties of the various materials of the package. Accordingly, the packages of the present invention exhibit little or no such warpage, and hence may be more easily and reliably mounted on a mother board, even where a plurality of the packages are stacked one on top of the other.
These and other aspects, features, and capabilities of the present invention will be clear from a reading of the following detailed description of the exemplary embodiments and the accompanying drawings.